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philips semiconductors 74f543 octal registered transceiver, non-inverting (3-state) 74f544 octal registered transceiver, inverting (3-state) product specification 1994 dec 5 integrated circuits ic15 data handbook
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 74f543 octal registered transceiver, non-inverting (3-state) 74f544 octal registered transceiver, inverting 93-state) 2 1994 dec 5 853-0874 14379 features ? combines74f245 and 74f373 type functions in one chip ? 8-bit octal transceiver with d-type latch ? 74f543 non-inverting 74f544 inverting ? back-to-back registers for storage ? separate controls for data flow in each direction ? a outputs sink 20ma and source 3ma ? b outputs sink 64ma and source 15ma ? 3-state outputs for bus-oriented applications ? 74f543 available in ssop type ii package description the 74f543 and 74f544 octal registered transceivers contain two sets of d-type latches for temporary storage of data flowing in either direction. separate latch enable (leab , leba ) and output enable (oeab , oeba ) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. while the 74f543 has non-inverting data path, the 74f544 inverts data in both directions. the a outputs are guaranteed to sink 24ma, while the b outputs are rated for 64ma. functional description the 74f543 and 74f544 contain two sets of eight d-type latches, with separate input and controls for each set. for data flow from a to b, for example, the a-to-b enable (eab ) input must be low in order to enter data from a0 - a7 or take data from b0 - b7, as indicated in the function table. with eab low, a low signal on the a-to-b latch enable (leab ) input makes the a-to-b latches transparent; a subsequent low-to-high transition for the leab signal puts the a latches in the storage mode and their outputs no longer change with the a inputs. with eab and oeab both low, the 3-state b output buffers are active and display the data present at the outputs of the a latches. control of data flow from b to a is similar, but using the eba , leba , and oeba inputs. type typical propagation delay typical supply current (total) 74f543 6.0ns 80ma 74f544 6.5ns 95ma ordering information description commercial range v cc = 5v 10%, t a = 0 c to +70 c drawing number 24-pin plastic skinny dip (300mil) n74f543n, n74f544n sot2221 24-pin plastic sol n74f543d, n74f544d sot137-1 24-pin plastic ssop type ii 74f543db sot340-1 input and output loading and fan-out table pins description 74f(u.l.) high/low load value high/low a0 - a7 port a, 3-state inputs 3.5/1.0 70 m a/0.6ma b0 - b7 port b, 3-state inputs 3.5/1.0 70 m a/0.6ma oeab a-to-b output enable input (active low) 1.0/1.0 20 m a/0.6ma 74f543 oeba b-to-a output enable input (active low) 1.0/1.0 20 m a/0.6ma 74f543 74f544 eab a-to-b enable input (active low) 1.0/2.0 20 m a/1.2ma eba b-to-a enable input (active low) 1.0/2.0 20 m a/1.2ma leab a-to-b latch enable input (active low) 1.0/1.0 20 m a/0.6ma leba b-to-a latch enable input (active low) 1.0/1.0 20 m a/0.6ma 74f543 a0 - a7 port a, 3-state outputs 150/40 3.0ma/24ma 74f543 b0 - b7 port b, 3-state outputs 750/106.7 15ma/64ma 74f544 a 0 - a 7 port a , 3-state outputs 150/40 3.0ma/24ma 74f544 b 0 - b 7 port b , 3-state outputs 750/106.7 15ma/64ma note: one (1.0) fast unit load is defined as: 20 m a in the high state and 0.6ma in the low state.
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 3 pin configuration 74f543 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 v cc b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 leba oeba eab leab oeab eba gnd sf00237 logic symbol (ieee/iec) 74f543 13 2 11 1 23 14 ien3 g1 1c5 2en4 g2 2c6 35d 4 6d 3 4 5 6 7 8 9 10 22 21 20 19 18 17 16 15 sf00239 logic symbol 74f543 11 23 14 1 eab eba leab leba v cc = pin 24 a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 13 2 22 21 20 19 18 17 16 15 345678910 sf00238 gnd = pin 12 oeab oeba
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 4 pin configuration 74f544 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 v cc b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 leba oeba eab leab oeab eba gnd sf00240 logic symbol (ieee/iec) 74f544 13 2 11 1 23 14 ien3 g1 1c5 2en4 g2 2c6 35d 4 6d 3 4 5 6 7 8 9 10 22 21 20 19 18 17 16 15 sf00241 logic symbol 74f544 11 23 14 1 eab eba leab leba v cc = pin 24 a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 13 2 22 21 20 19 18 17 16 15 345678910 sf00242 gnd = pin 12 oeab oeba function table for 74f543 and 74f544 inputs outputs status oexx exx lexx data 74f543 74f544 h x x x z z disabled x h x x z z disabled l l h z z disable + l l l z z disable + latch l l h h l latch + l l l l h latch + display l l l h h l trans p arent l l l l l h transparent l l h x nc nc hold h = high voltage level l = low voltage level h = high state must be present one setup time before the low-to-high transition of lexx or exx (xx=ab or ba) l = low state must be present one setup time before the low-to-high transition of lexx or exx (xx=ab or ba) = low-to-high transition of lexx or exx xx = ab or ba x = don't care nc = no change z = high impedance aoffo state
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 5 logic diagram for 74f543 qd le q d le detail a detail a x 7 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 oeab eab leab oeba eba leba 22 3 4 5 6 7 8 9 10 2 23 1 21 20 19 18 17 16 15 13 11 14 sf00243 v cc = pin 24 gnd = pin 12 logic diagram for 74f544 qd le q d le detail a detail a x 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 oeab eab leab oeba eba leba 3 4 5 6 7 8 9 10 2 23 1 22 21 20 19 18 17 16 15 13 11 14 sf00244 v cc = pin 24 gnd = pin 12
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 6 absolute maximum ratings (operation beyond the limits set forth in this table may impair the useful life of the device. unless otherwise noted these lim its are over the operating free-air temperature range.) symbol parameter rating unit v cc supply voltage -0.5 to +7.0 v v in input voltage -0.5 to +7.0 v i in input current -30 to +5 ma v out voltage applied to output in high output state -0.5 to +5.5 v i o current a pp lied to out p ut in low out p ut state a0 - a7, a 0 - a 7 48 ma i out c u rrent applied to o u tp u t in lo w o u tp u t state b0 - b7, b 0 - b 7 128 ma t amb operating free-air temperature range 0 to +70 c t stg storage temperature -65 to +150 c recommended operating conditions symbol parameter limits unit symbol parameter min nom max unit v cc supply voltage 4.5 5.0 5.5 v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i ik input clamp current -18 ma i o high level out p ut current a0 - a7, a 0 - a 7 -3 ma i oh high - le v el o u tp u t c u rrent b0 - b7, b 0 - b 7 -15 ma i o low level out p ut current a0 - a7, a 0 - a 7 24 ma i ol lo w- le v el o u tp u t c u rrent b0 - b7, b 0 - b 7 64 ma t amb operating free-air temperature range -0 +70 c
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 7 dc electrical characteristics (over recommended operating free-air temperature range unless otherwise noted.) symbol parameter test conditions 1 limits unit symbol parameter test conditions 1 min typ 2 max unit a0 - a7, v cc = min i oh = -3ma 10%v cc 2.4 v v oh high-level out p ut voltage a 0 - a 7 v cc = min v il = max i oh = - 3ma 5%v cc 2.7 3.4 v v oh high - level out ut voltage b0 - b7, v il = max v ih = min i oh = -15ma 10%v cc 2.0 v b 0 - b 7 v ih min i oh = - 15ma 5%v cc 2.0 v a0 - a7, v cc = min i ol = 24ma 10%v cc 0.35 0.50 v v ol low-level out p ut voltage a 0 - a 7 v cc = min v il = max i ol = 24ma 5%v cc 0.35 0.50 v v ol low - level out ut voltage b0 - b7, v il = max v ih = min i ol = 64ma 10%v cc 0.55 v b 0 - b 7 v ih min i ol = 64ma 5%v cc 0.42 0.55 v v ik input clamp voltage v cc = min, i i = i ik 0.73 1.2 v i i input current at maximum oeab , oeba , eab v cc = max, v i = 7.0 v 100 m a i i input voltage others v cc = 5.5, v i = 5.5v 1 ma i ih high-level input current v cc = max, v i = 2.7v 20 m a others 0.6 ma i il low-level input current eab , eba v cc = max, v i = 0.5v 1.2 ma i ozh + i ih off-state output current, high-level voltage applied v cc = max, v o = 2.7v 70 m a i ozh + i il off-state output current, low-level voltage applied v cc = max, v o = 0. 5v 600 m a i os short-circuit out p ut current 3 a0 - a7, a 0 - a 7 v cc = max 60 150 ma i os short - circuit out ut current 3 b0 - b7, b0 - b 7 v cc = max 100 225 ma i cch 70 105 ma 74f543 i ccl v cc = max 95 135 ma i cc su pp ly current (total) i ccz 95 135 ma i cc su ly current (total) i cch 80 110 ma 74f544 i ccl v cc = max 105 140 ma i ccz 100 135 ma notes: 1. for conditions shown as min or max, use the appropriate value specified under the recommended operating conditions for the ap plicable type. 2. all typical values are at v cc = 5v, t amb = 25 c. 3. not more than one output should be shorted at a time. for testing i os , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. otherwise, prol onged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. in any sequence of parameter tests, i os tests should be performed last.
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 8 ac electrical characteristics for 74f543 74f543 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test conditions v cc = 5.0v v cc = 5.0v 10% unit symbol parameter test conditions c l = 50pf r l = 500 w c l = 50pf r l = 500 w unit min typ max min max t plh t phl propagation delay a n to b n waveform 2 3.5 3.0 5.5 5.0 8.5 8.0 3.0 2.5 9.0 8.5 ns t plh t phl propagation delay b n to a n waveform 2 2.5 2.5 4.0 4.5 7.0 7.5 2.5 2.5 7.5 8.0 ns t plh t phl propagation delay leba to a n waveform no tag, 2 5.0 4.0 7.0 6.0 10.0 9.0 4.5 4.0 11.0 9.5 ns t plh t phl propagation delay leab to b n waveform no tag, 2 6.0 4.5 8.5 6.5 11.5 9.5 5.5 4.0 12.5 10.0 ns t pzh t pzl output enable time oeba to a n or oeab to b n waveform 4 waveform 5 2.0 3.5 4.0 5.0 7.5 8.5 1.5 3.0 8.0 9.0 ns t phz t plz output disable time oeba to a n or oeab to b n waveform 4 waveform 5 1.0 1.5 3.0 4.0 6.5 7.5 1.0 1.0 7.5 8.5 ns t pzh t pzl output enable time eba to a n or eab to b n waveform 4 waveform 5 4.5 5.0 7.0 7.0 10.5 10.5 4.0 4.5 11.5 11.0 ns t phz t plz output disable time eba to a n or eab to b n waveform 4 waveform 5 2.5 4.5 5.0 7.0 8.5 11.0 2.0 3.0 9.5 12.0 ns ac setup requirements for 74f543 74f543 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test conditions v cc = 5.0v v cc = 5.0v 10% unit symbol parameter test conditions c l = 50pf r l = 500 w c l = 50pf r l = 500 w unit min typ min max t s (h) t s (l) setup time, high or low a n to leab or b n to leba waveform 3 0.0 2.5 0.0 3.0 ns t h (h) t h (l) hold time, high or low a n to leab or b n to leba waveform 3 0.0 1.5 0.0 2.0 ns t s (h) t s (l) setup time, high or low a n to eab or b n to eba waveform 3 1.0 2.5 1.5 3.0 ns t h (h) t h (l) hold time, high or low a n to eab or b n to eba waveform 3 0.0 1.5 0.0 2.0 ns t w (l) latch enable pulse width, low waveform 3 4.0 4.5 ns
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 9 ac electrical characteristics for 74f544 74f544 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test conditions v cc = 5.0v v cc = 5.0v 10% unit symbol parameter test conditions c l = 50pf r l = 500 w c l = 50pf r l = 500 w unit min typ max min max t plh t phl propagation delay a n to b n or b n to a n waveform no tag 3.0 3.0 6.5 5.0 9.5 8.0 3.0 3.0 10.5 8.5 ns t plh t phl propagation delay leba to a n waveform no tag, 2 4.0 4.0 7.0 7.0 9.5 9.5 4.0 4.0 10.5 10.5 ns t plh t phl propagation delay leab to b n waveform no tag, 2 5.0 4.0 8.0 7.5 11.5 9.5 4.0 4.0 12.5 10.5 ns t pzh t pzl output enable time oeba to a n or oeab to b n waveform 4 waveform 5 2.0 3.5 4.0 5.5 7.0 8.5 1.5 3.0 7.5 9.0 ns t phz t plz output disable time oeba to a n or oeab to b n waveform 4 waveform 5 1.0 1.5 4.0 4.0 6.5 6.5 1.0 1.5 7.0 7.5 ns t pzh t pzl output enable time eba to a n or eab to b n waveform 4 waveform 5 4.0 4.5 7.0 8.0 9.5 11.0 3.5 4.5 10.0 12.0 ns t phz t plz output disable time eba to a n or eab to b n waveform 4 waveform 5 2.5 4.5 5.0 8.5 8.0 11.5 2.5 4.0 9.0 11.5 ns ac setup requirements for 74f544 74f544 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test conditions v cc = 5.0v v cc = 5.0v 10% unit symbol parameter test conditions c l = 50pf r l = 500 w c l = 50pf r l = 500 w unit min typ min max t s (h) t s (l) setup time, high or low a n to leab or b n to leba waveform 3 1.5 1.5 2.0 2.5 ns t h (h) t h (l) hold time, high or low a n to leab or b n to leba waveform 3 1.5 2.0 2.5 2.5 ns t s (h) t s (l) setup time, high or low a n to eab or b n to eba waveform 3 1.5 1.5 2.5 2.5 ns t h (h) t h (l) hold time, high or low a n to eab or b n to eba waveform 3 1.5 2.0 2.0 2.0 ns t w (l) latch enable pulse width, low waveform 3 4.0 4.5 ns
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 10 ac waveforms v m = 1.5v the shaded areas indicate when the input is permitted to change for predictable output performance. v m v m v m v m t plh t phl v in v out sf00245 waveform 1. propagation delay for inverting outputs v m v m v m v m t phl t plh v in v out sf00246 waveform 2. propagation delay for non-inverting outputs v m v m v m v m t h (l) t h (h) t w (l) v m v m t s (h) t s (l) a n b n a n b n leab , leba eab , eba sf00247 waveform 3. data setup time and hold times, and latch enable pulse width v m v m v m t phz t pzh v oh -0.3v 0v a n, b n a n, b n oeab , oeba eab , eba sf00248 waveform 4. 3-state output enable time to high level and output disable time from high level v m v m v m t plz t pzl v ol +0.3v a n, b n a n, b n oeab, oeba eab, eba sf00249 waveform 5. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification 74f543, 74f544 octal registered transceivers 1994 dec 5 11 test circuit and waveforms t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse t w amp (v) 0v 0v t thl ( t f ) input pulse requirements rep. rate t w t tlh t thl 1mhz 500ns 2.5ns 2.5ns input pulse definition v cc family 74f d.u.t. pulse generator r l c l r t v in v out test circuit for open collector outputs definitions: r l = load resistor; see ac electrical characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac electrical characteristics for value. r t = termination resistance should be equal to z out of pulse generators. t thl ( t f ) t tlh ( t r ) t tlh ( t r ) amp (v) amplitude 3.0v 1.5v v m r l 7.0v sf00128 test switch t plz closed t pzl closed all other open switch position
philips semiconductors product specification 74f543, 74f544 bus transceivers 1994 dec 05 12 dip24: plastic dual in-line package; 24 leads (300 mil) sot222-1
philips semiconductors product specification 74f543, 74f544 bus transceivers 1994 dec 05 13 so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1
philips semiconductors product specification 74f543, 74f544 bus transceivers 1994 dec 05 14 ssop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1
philips semiconductors product specification 74f543, 74f544 bus transceivers 1994 dec 05 15 notes
philips semiconductors product specification 74f543, 74f544 octal registered transceivers philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1994 all rights reserved. printed in u.s.a. (print code) date of release: july 1994 document order number: 9397-750-05135

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